1. Field of the Invention
The present invention relates to an integrated circuit comprising an electrically programmable data memory and means for executing commands for reading or writing in the memory.
2. Description of the Related Art
An embodiment of the present invention particularly relates to integrated circuits receiving transaction data, in particular integrated circuits for chip cards like electronic purses, telephone cards, transport cards, etc.
These transaction data having a monetary value and forming kinds of usable “tokens”, they are often fraudsters' targets who try to regenerate them after their use. FIGS. 1A to 1D schematically show an example use of a non-volatile memory of the electrically erasable and programmable type MEM1 to form a counter of transaction data, here a counter of the abacus type. Initially, the counter comprises a matrix of bits bi,j, each bit having an initial value, for example four lines of bits equal to 0, each bit bi,j belonging to a ith horizontal line and a jth vertical line and representing a transaction unit. Each time a unit is used, a bit is irreversibly set to 1 beginning for example with the first bit on the right of the upper line, then passing from one line to another when the units of a line have been used. FIG. 1B shows the aspect of the counter after 3 units have been used, FIG. 1C the aspect of the counter after 7 units have been used and FIG. 1D the aspect of the counter once all the units have been used.
Each bit bi,j is stored by a memory cell and the change from the initial value of the bit to the “used” value, here from 0 to 1, is obtained by having the memory cell changing from an erased initial state to a programmed state. Thus, a fraudster wishing to regenerate the value of the units counter will try to erase the memory cells in the programmed state so that all the units of the counter are reset to 0. To that end, the erasure technique most commonly used is the collective erasure of memory cells, by exposing the memory MEM1 to a particle beam, usually a UV beam (beam of ultraviolet light). This UV beam has the effect of extracting electric charges from memory cells and bringing them into an electrical state called “UV state”.
That will be better understood by referring to FIG. 2 which shows an example of electrically erasable and programmable memory cell Ci,j allowing a bit bi,j to be stored. The memory cell Ci,j comprises a floating gate transistor FGT and an access transistor AT, both of the NMOS type. The access transistor has a drain terminal D connected to a bit line BLj, a gate G connected to a word line WLi and a source terminal S connected to a drain terminal D of the transistor FGT. The latter further comprises a floating gate FG, a control gate CG linked to a gate control line CGL, and a source terminal S linked to a source line SLi.
The memory cell Ci,j is set into the programmed state for example by applying a voltage Vpp on the drain terminal D of the transistor FGT, via the access transistor AT, and a voltage of lower value, for example 0V, to its control gate CG. Electric charges are injected into the floating gate FG and lower the threshold voltage Vt of the transistor FGT, which generally becomes negative. The memory cell Ci,j is set into the erased state for example by applying the voltage Vpp to the control gate CG of the transistor FGT and a voltage of lower value, for example 0V, on its source terminal S. Electric charges are extracted from the floating gate FG and the threshold voltage of the transistor FGT increases to generally become positive.
The reading of the memory cell Ci,j is ensured by a read circuit RCTj linked to the drain terminal D of the transistor FGT via the bit line BLj and the access transistor AT. The circuit RCTj applies a bias voltage Vpol to the bit line while a read voltage Vread is applied to the control gate CG of the transistor FGT. If the transistor FGT is in the programmed state, the memory cell is conductive and a read current Iread superior to a determined threshold is flowing through the bit line BLj. The read circuit RCTj then supplies a bit bi,j whose value is defined by convention, for example 1. If the transistor FGT is in the erased state, the memory cell is not conductive or little conductive and the read circuit RCTj supplies a bit bi,j of inverse value, here a bit equal to 0.
The read voltage Vread thus plays an important role in determining the value of the bit bi,j and is superior to the threshold voltage Vtp of the transistor FGT in the programmed state and inferior to the threshold voltage Vte of the transistor FGT in the erased state. That appears clearly in FIG. 3 which shows a statistical distribution curve CP of threshold voltages Vtp of memory cells in the programmed state and a statistical distribution curve CE of threshold voltages Vte of memory cells in the erased state, the ordinate axis representing a statistical number N of memory cells. The curve CP is comprised between two negative threshold voltages Vtp1, Vtp2, for example −1.5V and −3.5V, and the curve CE is comprised between two positive threshold voltages Vte1, Vte2, for example 1V and 3V. Between the two distribution curves CE, CP, there is a statistical distribution curve CUV delimited by the threshold voltage Vtp1 on the left and by the threshold voltage Vte1 on the right. This curve CUV represents the statistical distribution of the threshold voltages of memory cells which have been erased by a UV beam and being in the UV state. Thus, the UV erasure does not have the same effect as the electrical erasure, since the cells have threshold voltages neither corresponding to a threshold voltage of an electrically programmed floating gate transistor nor to a threshold voltage of an electrically erased transistor.
The solution usually chosen to counter a fraudulent UV erasure consists in using a read voltage Vread located on the right of the statistical distribution curve CUV, for example the voltage Vte1 in FIG. 3 (the curves CUV, CE being contiguous here). Thus, any memory cell which has been erased by UV and read by the voltage Vread=Vte1 is in the conducting state and is seen by the read circuit as a programmed memory cell.
However, a read voltage that high results in memory cells becoming highly conductive (low serial resistance) during the read phases, and causes an increase of power consumption. Moreover, the read voltage must stabilize and propagate through conducting paths before being applied to memory cells, which implies a not negligible waiting time after powering on the integrated circuit before being able to read data. Lastly, the read voltage being close to the threshold voltages of erased memory cells (curve CE), any shift of the threshold voltage of an erased memory cell beyond the read voltage is rendered by a read error. This solution thus causes the read process to be sensitive to retention loss in the erased memory cells.
Another solution, described by EP 1 006 532, is to provide a reference memory cell which is placed in an erased or programmed initial state and is then read by two read voltages, in order to detect whether the memory cell actually is in the initial state or in an intermediate state corresponding to the UV state. The drawback of this solution is to require two read voltages, one being a “standard” read voltage and the other making it possible to detect whether the memory cell is in the UV state.